Setting log file to 'E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/project/xo2/verilog/xo2_verilog/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.6_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c.v
(VERI-1482) Analyzing Verilog file E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_clk.v
(VERI-1482) Analyzing Verilog file E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_rreg.v
(VERI-1482) Analyzing Verilog file E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_st.v
(VERI-1482) Analyzing Verilog file E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_wreg.v
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c.v(72,8-72,11) (VERI-1018) compiling module i2c
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c.v(72,1-213,10) (VERI-9000) elaborating module 'i2c'
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_wreg.v(53,1-142,10) (VERI-9000) elaborating module 'i2c_wreg_uniq_1'
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_rreg.v(53,1-99,10) (VERI-9000) elaborating module 'i2c_rreg_uniq_1'
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_clk.v(58,1-99,10) (VERI-9000) elaborating module 'i2c_clk_uniq_1'
INFO - E:/FPGA_Example/i2ccontrollerforserialeeproms/rd1006_i2c_controller_for_serial_eeproms/rd1006/source/verilog/i2c_st.v(56,1-297,10) (VERI-9000) elaborating module 'i2c_st_uniq_1'
Done: design load finished with (0) errors, and (0) warnings